ReRAM technology is complex and multi-faceted, encompassing expertise from an array of disciplines. Since the early 2000s, when the industry first saw that Flash would ultimately have scaling issues, many companies have tried – and failed – to deliver a commercial replacement for Flash.
Now, as we see the world’s leading foundry placing its NVM bets for the future on Resistive RAM (ReRAM or RRAM), I thought I would share what goes into creating such a technology.
To be able to bring up a successful ReRAM technology that is both optimized for performance and commercially viable, a company requires four key elements. With only one or two or even three of these ‘pillars’ of success, a company cannot provide a strong technology which fully addresses the needs of the market. Each of these pillars represents a domain of expertise that is inherent to developing and optimizing the solution, and each domain requires a very different skillset and know-how.
In this article, I will describe these four pillars, explain how each contributes to enhancing the technology and how, when combined under the same roof, results in an optimized solution.
Above: The ‘pillars’ of ReRAM success
Device physics is the first pillar for a successful solution. At Weebit this team works on researching and developing better and more disruptive memory devices, by optimizing the ReRAM bitcell and its select device. The team focuses on the interaction between currents, voltages and resistance targets for the optimal cell, and the materials required to create it. This is part of the Weebit ‘secret sauce,’ comprising our unique recipe of the memory stack that we can tweak for specific applications. Within this area, there are many knobs to adjust for optimal results, and Weebit has 13 PhDs focused on this, joined by additional researchers from CEA-Leti.
The second key pillar is process. This team focuses on how to manufacture the cell efficiently using a specific fab’s tools, technologies, and materials, etc. This includes perfecting the memory stack, ensuring quality control of the layers, meeting a uniform process window, and achieving high production yield. In this area, we can tune numerous knobs including the wafer processing equipment, tools and conditions, number of masks and more. This team is also responsible for the integration of our unique recipe into an existing process flow of our customers, avoiding any impact on existing devices and minimizing the effort.
While there is always a plan of record (POR) that is ready and qualified, it can be further enhanced per fab and per application, and all the data we accumulate is used for future enhancement.
Analog design is another key pillar. This team assembles thousands and millions of bits into one big memory array, and builds the surrounding logic which controls it in the most efficient way, making sure that the currents and voltages delivered are stable and uniform. Among other circuits, the team designs patent-pending fast-wakeup circuitry, which ensures overall system efficiency, as well as voltage regulators, and circuits which minimize the wear of writing to the cells, increasing the endurance. This team also ensures high power efficiency in our ReRAM periphery circuitry, both from static and active power perspectives, eliminating any unneeded overhead power beyond the power of the bitcells.
Digital design is another key pillar for creating a successful NVM technology like ReRAM. It serves as the interface between the memory array and the rest of the system, which is digital by nature. Digital designers focus on creating algorithms and digital solutions to optimize parameters like programming current and voltage, read and standby power modes, and more. They also try to minimize the number of writes into a cell, for example avoiding unnecessary programming of bits, thus increasing the endurance. Designers work in strong collaboration with the device team so the algorithms address and solve every potential failure mechanism in the memory cell.
My colleague Ilan Sever discussed Weebit’s design expertise in the recent article, “ReRAM Gets a Boost from Smart Algorithms.”
So how does this combination of expertise play out in tangible ways? Let’s look at a couple of applications, specifically how each of our teams at Weebit contributes to meeting such requirements, and how they augment each other to reach optimized solutions.
Optimizing for specific applications
First, let’s consider an ultra-low-power application like an internet of things (IoT), Bluetooth® Low Energy (BLE), medical wearable or other battery-operated device. Such a device needs a low-voltage and low-power design, energy-efficient programming, operation out of standard I/O or lithium battery voltage, and in some cases it will limit the total peak power that can be consumed at any moment. The NVM must have fast wake up and fast switching between modes to take advantage of every cycle before power-down. Depending on the specific application – like implantables – there may be even stricter low power requirements.
On the other end of the spectrum, let’s consider a high-temperature device like an engine control integrated circuit (IC) in automotive. Creating a device optimized to work in high temperatures presents a very different challenge compared to meeting the requirements of our low-power application, even though it needs to be optimized for power consumption too. An NVM for this application must work reliably for up to 20 years at temperatures up to 150 or even 175 degrees Celsius with very low DPM (defects per million) and high endurance. High temperatures are a challenge for all memories, due to the impact on the materials they are built of, resulting in potential data loss, slower speeds and power leakage.
For the ultra-low-power application, our device team focuses on optimizations such as modifying the memory stack to reduce bit cell programming power and lowering the read and program voltages. For the high-temperature application, they might select materials for minimal drift over time, with lower energy and slower migration. All these device optimizations must be done in close collaboration with the process team, making sure that the modified stack can be reliably, repetitively and cost-effectively manufactured, and provide high yield. This is where the science of physics meets the science of chemistry.
But it doesn’t end there. When looking at the low-power application, our analog team designs analog circuitry with lowest power overhead during read/write activity and the lowest sleep and standby power consumption. For the high-temperature application they design circuits to withstand such temperatures.
Finally, our digital team introduces power-aware smart programming algorithms and low-power ECC algorithms for the ultra-low-power application, and crafts temperature-aware algorithms using an on-chip temperature sensor for our high-temperature application. Such algorithms are closely developed with the analog and device teams early in the cycle.
Precise characterization and rigorous testing ensure continuous improvements across all these areas. Our test and characterization team identifies any issues and goes back to the other teams to find workaround solutions, enabling adjustments that lead to higher reliability and higher yield. With any issue that is faced, the teams can quickly go to the lab to test out solutions. Having this expertise in-house like we do at Weebit means there is a very short loop. To learn more about this process, check out the article, “The Importance of Character Development: Semiconductor Characterization Explained. The Importance of Character Development: Semiconductor Characterization Explained
Working together
Each team has special contributions, and the value of working together between the teams and with test/characterization in a fast and efficient manner is incalculable.
Within each of the pillars, there are numerous knobs that the team can adjust to impact their specific domain. But they also must work together to find the balance between these adjustments. Every time one adjustment is made, whether it be in terms of stack modification, temperature, algorithm, voltage or some other parameter, it can, and normally will, affect something else.
For example, if the analog team is optimizing for low power and wants to reduce the voltage level required for a Read operation, there are also changes that must be made to the memory stack itself since the current will be different. This means the device team must be involved. And it might also impact the manufacturing process, so they need to pull in the process team. And so on.
The key is understanding the specific customer, their application and priorities. For each application, we can adjust many knobs to come up with an optimized solution, beyond our existing qualified POR. Because we have all this expertise in-house, we can do this seamlessly. If a company only has analog and digital design expertise (but no process or device teams) they will only be able to adjust the analog and digital knobs; they won’t be able to make modifications to the core technology like Weebit can.
We believe that Weebit is the only independent ReRAM company that has such a combination of in-house expertise, and this will enable Weebit to become the leading independent provider of ReRAM for a new generation.
