Low-power design is critical, especially for chips inside battery-operated IoT devices that must support applications for several years on one battery in a very small area. Embedded non-volatile memory (NVM) for these devices must have ultra-low-power, high endurance and high reliability to support continuous monitoring, logging and communicating of small amounts of data over the product’s lifetime.
Ultra-low-power embedded NVM like Weebit ReRAM (RRAM) can enable longer use times between recharges or battery replacements and help improve system energy efficiency. The low voltage levels used for memory transactions, coupled with ReRAM’s fast memory access time, greatly reduce power consumption. And with programming, standby, sleep, and very deep power-down ReRAM modes, as well as rapid wake-up from deep power-down, designers can enable near-zero leakage power of internal and external NVM. You can read more about this in my previous article, ‘How Low Can You Go? An Inside Look at Weebit ReRAM Power Consumption’.
By reducing power consumption, the memory subsystem can also allocate more power to other critical components to enhance overall system performance. Designers can take this advantage even further by implementing smart, power-aware system memory partitioning strategies. This includes dividing data intelligently across volatile and non-volatile memory resources to reduce the size of system SRAM.
Smart memory partitioning in practice
In a wearable sensor designed to monitor a specific health parameter, it is common to store code on external flash and then load code onto the local code SRAM from which the MCU then fetches the code. Each time the system wakes up to log and process data, there is MCU power consumption related to executing the Write cycles; as well as time and energy needed to load the code from the external flash into the code SRAM, and for the MCU to fetch the code. There is also power required to maintain the code SRAM or keep on the always-on logic for these operations.
Above: Typical MCU architecture with external flash
An alternative way to architect this would be using an eXecute in Place (XiP) architecture where on-chip ReRAM can be used to store code instead of the code SRAM, and the MCU can fetch the code directly from the ReRAM. This reduces system wake-up time and decreases power since there is no need to access the external flash. It is also possible to turn off the code ReRAM to further reduce power. Our calculations show that this can result in 30% power savings over the previously described traditional architecture.
In addition, instead of storing log data to external flash, we can store it into on-chip ReRAM, eliminating the external flash altogether. If we replace the on-chip code SRAM as well as part of the data SRAM with ReRAM, we can achieve a total of 60% power reduction, and a device that can last up to four years!
Finally, instead of logging the data into SRAM and storing processed data onto ReRAM, we can log processed data directly into ReRAM, thereby eliminating most of the on-chip SRAM. In this way we can reach a total of more than five years of lifetime for this application. With NVM like ReRAM, there is close to zero power consumption needed to retain the data during inactive states.
Above: Example medical device logging system with on-chip ReRAM for code and data
Enabling new use cases
Reconsidering the memory technology and architecture in a typical IoT sensor/medical logging device can enable advantages in terms of power consumption and device lifetime. This becomes even more important with a device that doesn’t have a battery. In a device using energy harvesting, a traditional architecture can be prohibitive. Using a combination of logging data in SRAM and uploading it to flash can actually consume more power than what’s available!
Advanced hearing aids, wireless earphones, pacemakers and other medical and wearable appliances that need over-the-air (OTA) firmware updates can also benefit. In our calculations, performing a chip erase and then programming the new code required for the OTA update requires more time and energy than what is available using a standard off-the-shelf ultra-low-power flash device.
Embedded NVM like ReRAM, coupled with smart memory partitioning, can improve the energy efficiency of battery operated and energy-harvesting ICs. In a new article in Electronics Weekly, I go into greater detail on the different architectures and power savings that can be achieved.
