In AI inference, trained models apply their knowledge to make predictions and decisions. To achieve lower latency and better security, the world is transitioning steadily towards performing AI inference at the edge – without sending data back and forth to the cloud – for a wide range of applications.

Because edge devices are often small, battery-powered, and resource-constrained, it’s important that the computing resources enabling this process and the associated memories are ultra-low-power and low-cost. This is a challenge for AI workloads, which are known to be power-hungry.

The industry has been making progress towards lower power computation largely by moving to more advanced process nodes. This enables more performance with greater energy efficiency in smaller silicon area. However, non-volatile memories (NVMs) haven’t been able to scale to advanced nodes along with logic. Today we see advanced chips in process nodes of 3nm. At the same time, embedded flash memory is unable to scale below 28nm. This means that NVM and AI engines are often manufactured at very different process nodes and can’t be integrated on the same silicon die.

This is one of many reasons why the industry is exploring new memory technologies like Weebit ReRAM (RRAM).

The need for a single-die solution

Neural Network coefficients (often referred to as NN weights), which are used for computations by the inference engine, need to be stored in an NVM, so that when the system is powered-on these coefficients are available for compute workloads. Because it’s not possible to integrate flash and an AI engine on one die below 28nm, it is standard practice to implement a two-die solution, with one die at a small process node used for computing, and the other die at a larger process node used for storing the coefficients. These two dies are then either integrated in a single package or in two separate packages. Either way, such a two-die solution is more expensive and has a bigger footprint. Also, copying the coefficients from an external flash to an on-chip SRAM in the AI chip is very power hungry and creates latencies. In addition, the fact that the coefficients are moved from one chip to the other creates a security risk, as it is easy to eavesdrop this communication.

The ideal solution for edge AI computing from power, latency, cost and security perspectives is a single die that hosts both memory and compute.

A scalable, single-chip solution with ReRAM

Embedded ReRAM is the logical alternative to flash for edge AI. ReRAM is significantly more energy efficient than flash, and it provides better endurance and faster program time. Since it is scalable to advanced processes, ReRAM enables a true one-chip solution, with NVM and computing integrated on the same die.

ReRAM-enabled SoCs are less expensive to manufacture because they only require two additional masks in the manufacturing flow, while flash requires 10 or even more such masks. Embedding ReRAM into an AI SoC would eliminate the need for off-chip flash devices and replace most of the large on-chip SRAM used to temporarily store the NN weights. Since the technology is non-volatile, the system can boot much faster as there is no need to wait for loading the AI model and firmware from external NVM, and the security risk is removed. ReRAM is also much denser than SRAM, so more memory can be integrated on-chip to support larger neural networks for the same die size and cost, while enabling more advanced AI algorithms.

New Demo: ReRAM for ultra-low-power edge AI

A new demonstration showcases the advantages of Weebit ReRAM-powered edge AI computing. Developed through a collaboration between Weebit and Embedded AI Systems Pte. Ltd. (EMASS), a subsidiary of Nanoveu, the gesture recognition demo shows Weebit ReRAM working with EMASS’s energy-efficient AI SoC, the EMASS ECS-DOT. The demo emphasizes the ultra-low-power consumption of ReRAM and its ability to enable instant wake-up AI operations. In the real world, such a system could be used to detect driver activity for advanced driver safety systems, or it could be used for safety/surveillance, robotics, and many other applications.

ECS-DOT is an edge AI chip manufactured in a 22nm process that delivers significant energy efficiency and cost advantages, with best-in-class AI capacity. In the demo, ECS-DOT loads the neural network weights from Weebit ReRAM where they are being stored. As noted earlier, this is a powerful feature of ReRAM – it can be used to replace the large on-chip SRAM to store the NN weights, as well as the CPU firmware.

Weebit ReRAM isn’t yet integrated into the ECS-DOT SoC, so the proof-of-concept demo shows a two-chip solution with the 22nm Weebit demo chip communicating with the EMASS chip over an SPI bus. In an end solution, the ReRAM would be integrated on-chip, eliminating latency, cost and security risks, and demonstrating even lower power consumption. Such integration can enhance system performance and also ensure scalability and sustainability, paving the way for smarter, more autonomous edge devices.

Above: ultra-low-power ReRAM based gesture recognition system
with Weebit ReRAM and EMASS AI SoC

EMASS recently made a strategic pivot away from MRAM technology and is embracing ReRAM. The company says that ReRAM is better able to support next-generation systems in IoT, automotive, and consumer electronics.

Looking Ahead

Research is now underway to bring memory and compute resources even closer together through analog in-memory compute. In this paradigm, compute resources and memory reside in the same location, so there is no need to ever move the coefficients. Such a solution using ReRAM will be orders of magnitude more power-efficient than today’s neural network simulations on traditional processors.

You can see our new demo video here:

The post ReRAM-Powered Edge AI:<br>A Game-Changer for Energy Efficiency, Cost, and Security appeared first on Weebit.

You might have seen the news that Weebit’s second Weebit ReRAM IP module is now available for the S130 CMOS process from SkyWater Technology. The IP is now fully qualified per JEDEC standards and is ready for mass production. We recently filmed a quick demonstration of the IP module to show that it’s functional, fast, and much lower power than flash.

You can watch the video by clicking below.

In the first part of the demo, we took a photo, added a Weebit logo, and saved it to the module—storing the image as ones and zeroes in the memory. As you watch the demo, take note of the energy consumption used to complete the Write operation, along with the comparison to typical NOR flash memory. You’ll see that Weebit ReRAM uses 0.23 millijoules of energy to complete the Write operation, while typical flash takes 33.0 millijoules for the same Write operation. The difference between the energy consumed by ReRAM compared to flash on the same operation is more than 100X!

There is a similar difference on Read energy, with Weebit ReRAM consuming 0.72 microjoules and flash consuming 28 microjoules – a ~40X difference!

After the photo has been stored once, we save it again. This time, the only thing that has changed in the image is the clock in the upper right corner. Because Weebit ReRAM has direct program capability and byte addressability, it only needs to actively store the new bits of the image – in this case the numbers on the clock. Parts of the image where data did not change require very little time and energy to access, and parts where new data was written require a bit more. You can see that it took 55.1 milliseconds to store the original image, and when stored with the small change, it only took 3.7 milliseconds.

Direct program capability and byte addressability are key differentiators compared to flash, which must access entire sectors of data every time it erases or writes. Looking at Write energy consumption, you can again see the advantage compared to flash: Weebit only consumed 0.02 millijoules for the operation, while the NOR flash would consume 2.2 millijoules for the same operation – a difference of 100X!

If you’d like to learn more about the low power consumption of Weebit ReRAM (or RRAM), check out our new article, How Low Can You Go? An Inside Look at Weebit ReRAM Power Consumption. And stay tuned for future videos and articles where we discuss this important topic.

The post Functional, Fast, and Ultra-Low Power:<br>A Live Look at Weebit’s Second IP Module appeared first on Weebit.

What is a PMIC?

One of the first things to know about a PMIC is how to say it. You can say each letter separately, or you can call it a “P-mick”. At only two syllables, it’s easier to say, and if you’re reading this article aloud to your colleagues, they’ll be very impressed by your knowledge.

PMICs are integrated circuits (ICs) that regulate and control the power in an electronic system and often incorporate multiple power management functions in one chip.  For mobile and other battery-operated devices like wearables, hearables, sensors, and IoT devices, PMICs can help extend battery life, decreasing battery size to achieve the smallest possible form factor. In high-performance, computationally intensive platforms, PMICs are used to maximize performance per watt while increasing system efficiency.

A PMIC is responsible for controlling the flow and direction of electrical power within a device

PMICs are ubiquitous – they are used in just about every electronic system. At the most basic level, the PMIC controls the flow and direction of electrical power within a system. It sets the voltage levels (e.g., 3.3V, 5V, etc.) for each of the chips in a system, including CPUs, digital-to-analog converters (DACs), analog to digital converters (ADCs), and input/output (I/O) devices. Because voltage often varies between these components, many products use multiple voltages internally, and the PMIC makes sure the correct voltage is supplied to each one. The PMIC also acts as a conduit from the external power source – such as a battery or wall outlet – to the various components.  Because of the combination of functionality that is required in a PMIC, a BCD (Bipolar-CMOS-DMOS) technology is often used. This single process makes it possible to integrate analog components (bipolar), digital components (CMOS) and high-voltage transistors (DMOS) on the same die.  This is a complex technology that provides advantages for PMICs and a large set of analog and power components to the designer.

All this means that a PMIC’s job is more challenging in more complex products. Today, PMICs for complex systems have pre-programmed and adjustable functions to address the many disparate requirements they may face, and they are often field upgradeable as well.

A Growing Market

According to a 2021 report from Yole, the PMIC market will grow to more than US$25.6 billion by 2026, with mobile/consumer representing the largest segment. Multi-channel PMICs – those that need various voltages to power various loads – are dominant in these markets.

The same report predicts automotive and industrial applications will grow most quickly during that time. In automotive, this is driven by adoption of multi-channel PMICs widely used in advanced driver assistance systems (ADAS), as well as electric vehicles where PMICs manage the power flow through the EV battery.

There are also opportunities for highly integrated PMICs in other segments such as industrial, telecom, and medical applications.

NVM in PMICs

Power management as a function has been used for decades. Up until the mid-1990s, the primary goal was to trim voltages to fit product requirements, and this was handled as a simple analog function. In the mid-1990s, as electronic complexity increased, PMICs began to manage this function using very simple EEPROM, a basic type of read-only Non-Volatile Memory (NVM) to store analog calibration and trimming data. One-Time-Programmable (OTP) NVM was also used for this function, but since trimming often requires iterative voltage adjustments, multiple banks of NVM were needed when using OTP.

Starting in the early 2000s, as companies started integrating more and more digital functionality into one chip (a System-on-a-Chip or SoC) to meet performance, cost and power consumption goals, the function of the NVM inside of PMICs began to evolve and it continues to do so today. While still used for trimming voltages, in today’s highly integrated SoCs, embedded NVM is a critical block within the PMIC, used to store controller code and configuration data, as well as unique IDs.

Some PMICs today also require integration of a microcontroller (MCU) for added intelligence, including smart sensing and measurement in ultra-low power IoT products. These highly integrated systems not only need to store data and boot code, but must also run firmware updates, requiring high-performance, low-power NVM.

As NVM plays an increasingly critical role in these chips, it has moved from storing hundreds of bits to thousands of bits to tens of thousands of bits – potentially even a million bits.

Of course, not every PMIC needs this level of complexity. Some systems need only very simple voltage regulation, and simple PMICs with small NVM can do this. This is why NVM for PMICs can range from very simple EEPROM or OTP NVM for small, simple requirements; to Multiple-Time Programmable (MTP) for a small programmable/reconfigurable NVM; to embedded flash for more robust needs. There are power, area, performance and cost tradeoffs which designers must consider alongside power management requirements.

Embedded Flash in PMICs

When it became apparent in the early 2000s that a more robust NVM solution was needed for a growing number of PMICs, embedded flash was the only available option, so that’s the way the industry moved. Unfortunately, the addition of flash introduced a great deal of complexity and expense, starting with the addition of between seven and 11 extra masks into an already complex manufacturing process.

Another complication is that embedded flash must be integrated in the Front End of Line (FEOL) of the manufacturing process where other analog and power components are also integrated. Because the BCD process integrates a variety of different components on a single die, it requires careful balancing of the different design needs of each device type.

At the same time, Flash requires careful integration to make sure it works reliably within a design – often based on past experience and best practices. To accommodate it, companies must make technology design trade-offs that sometimes compromise the other analog components in the FEOL. In this way, flash plays an outsized role in driving the integration strategy of the whole chip. This is obviously not ideal since the compromises designers must make to accommodate flash can lead to overall degraded performance, larger size, and higher cost.

Flash has other limitations including a lack of robustness in harsh environments, which often requires building costly redundancy into the design. Importantly, the integration cost of embedded flash increases with each process shrink, an obvious challenge as companies move to more advanced process geometries. All this means that the industry is looking for new NVM solutions.

Emerging Memories for PMICs

When considering alternatives, the first consideration is whether an NVM is integrated in the back-end-of-line (BEOL), where no compromises are needed with other analog components. Using a BEOL NVM allows full optimization of analog components, and it simplifies adoption into new fabs (it can be adopted once for a geometry and it will work with all the different variants, unlike flash which must be adapted to each variant). A BEOL memory is the best alternative to embedded flash for PMICs, but it must be small and cost-effective.

Weebit ReRAM is a Back-End-of-Line (BEOL) technology, enabling full optimization of analog components, and simplifying adoption into new fabs

As a BEOL NVM technology, Ferroelectric RAM (FRAM) is one option that companies can consider. However, FRAM is unable to handle the high temperatures needed in PMICs (up to 150 degrees Celsius). It also requires exotic materials and new fab equipment – neither of which makes sense for an analog chip like a PMIC. Another option is Magnetoresistive RAM (MRAM). MRAM is also a BEOL technology and, in most cases, it can handle high temperatures. However, MRAM is complex and expensive from a capital expenditure as well as manufacturing standpoint, requiring expensive additional tools and masks, which is not a good fit for the analog market.

The answer? Weebit ReRAM. As a small and cost-effective BEOL technology, it checks all the boxes for NVM in PMICs.

Weebit ReRAM checks all the boxes for NVM in PMICs

Toward Net Zero

The low power consumption of Weebit ReRAM is an important advantage for PMICs, especially as societies across the world look for ways to decrease their carbon footprints. PMICs can keep power consumption and dissipation in electronic systems as low as possible – both active (when it’s on) and leakage (when it’s off). With PMICs designed from top to bottom for high efficiency – including ultra-low-power NVM, it’s possible to have a real impact on this critical issue.

Weebit and our R&D partner CEA-Leti are currently conducting an environmental initiative that will analyze the environmental impact of Weebit’s ReRAM compared to other NVM technologies.

With its unique combination of advantages, Weebit ReRAM is the logical alternative to embedded flash for the next generation of PMICs.

The post The Power of ReRAM for PMICs appeared first on Weebit.

There is high demand to scale memory nodes further for applications like microcontrollers (MCUs) for automotive and other markets, as well as artificial intelligence (AI) applications. This is driving the industry search for non-volatile memory (NVM) alternatives to embedded flash.

Memories that are integrated in the back end of line (BEOL) of the manufacturing process like ReRAM are attracting growing interest because, unlike flash, these memories don’t interfere with the integration of analog components in the front end and are therefore easier to integrate with the design. With its faster speed, lower power consumption and lower additional mask count compared to flash memory, ReRAM is increasingly of interest to the industry, and great strides are being made in its development into a mature technology.

Together with CEA-Leti, Weebit recently published a paper, “High temperature stability embedded ReRAM for 2x nm node and beyond,” outlining performance results of Weebit ReRAM in 28nm. The results highlight some of the many advantages of Weebit ReRAM. We presented these results at the recent International Memory Workshop (IMW) 2022.

High temperature stability

For many applications such as automotive, aerospace and defense and others, memory retention and stability at high temperatures is critical. In ReRAM technologies, retention failures are usually caused by filament dissolution resulting from motion and recombination of oxygen vacancies, which happens as temperatures increase, causing the atoms to move. This can cause the filament to become less conductive or to dissolve, leading to increased resistance of the memory cell.

Weebit has optimized the materials and engineered the Weebit ReRAM stack to limit the motion of the oxygen vacancies caused by increased temperatures, making the filament more stable over time.

Our results show that Weebit ReRAM in 28nm achieves a low raw bit error rate (BER) without any need for error correcting code (ECC) or redundancy. Specifically, we show the ability of Weebit ReRAM to maintain a stable memory window after 15 hours’ bake at 210°C after 10,000 cycles. To the best of our knowledge, this is one of the best results ever reported for any company’s ReRAM.

Image: Weebit ReRAM maintains a stable memory window after 15 hours’ bake at 210°C after 10,000 cycles (without using a Program & Verify algorithm).

The importance of endurance

While endurance of 10,000 programming operations is sufficient to address many applications today, endurance above 100,000 operations is required for any NVM to be a contender for next-generation applications, with some applications even requiring up to 1 million operations.

In ReRAM technologies, endurance failures happen when the resistance window narrows. This can happen when there is degradation (of the dielectric material on the switching layer due to defect generation. This can cause resistance to drop to an intermediate resistance between the High Resistive State (HRS) and Low Resistive State (LRS) or be stuck at the LRS.

Image: In the ReRAM forming step, a positive voltage is applied on the switching layer, creating the filament and changing the resistance of the oxide layer to LRS (read more here). Endurance failures happen when the resistance window collapses.

In any NVM, as the number of Program/Erase cycles increases, endurance failures may occur. To avoid this, it’s critical to make optimizations such as adjusting programming conditions, optimizing the programming energy, and trading off with the window margin.

Since electrical current flowing through the dielectric degrades that material over time, the key is to provide enough current to create a robust filament, but no more energy than that. Because we know how parameters such as voltage and time will impact the resistance window, we’ve made optimizations in Weebit ReRAM to ensure we are providing enough current to create the filament but not wasting energy that can degrade the dielectric. We filed for several patents related to how we implement these optimizations.

In our paper, we show that Weebit ReRAM can endure more than 10⁵ cycles with no memory degradation, and no failure on 16kb arrays. This was achieved based on a single programming pulse without using a program and verify (P&V) algorithm (which would have enabled adjustments to be made throughout the cycling). The results are based on raw data, reflecting the intrinsic quality of the Weebit ReRAM technology and memory stack. In addition, 10⁶ cycles are achievable with some optimizations.

Other Key Findings

The new paper outlines many other findings based on a wide array of tests. One example is testing for solder reflow compliance. Since most assembly processes require short bursts of very high-temperature soldering (up to three cycles), it’s critical that the NVM retain its programmed data during this process. NVM technology must sustain the Pb-free solder reflow profile as described on JEDEC standards (IPC/JEDEC J-STD-020D.1), with a 260°C temperature peak. Weebit ReRAM passed basic (3x reflow) and extended (9 cycles) SMT (Surface Mount Technology) tests with zero failures.

In addition to tests that show raw data – highlighting the intrinsic performance aspects of Weebit ReRAM – we also showed how technology enhancements and forming protocol optimizations can optimize device performance. And the paper highlights the results we achieved using a P&V (Program and Verify) algorithm. In a real product, such an algorithm is used to make optimizations/reprogramming tweaks after each programming operation. Using a P&V algorithm, Weebit ReRAM achieved a clear window margin with zero failures on a 1Mb array.

The conclusion of all of our tests show that Weebit ReRAM is a highly reliable ReRAM technology when integrated in 28nm. As we continue our progress toward productization, and also work on 22nm and below, these results go a long way in showing that customers can be confident in engaging with Weebit for next-generation designs.

Read the paper.

By Gabriel Molas, Weebit Chief Scientist

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