When people think of semiconductor companies, they often picture vast factories filled with billion-dollar equipment. But Weebit Nano operates in a very different way.

If you’ve read our blog before, then you know that we develop Resistive RAM (ReRAM / RRAM), an advanced non-volatile memory (NVM) technology designed for a new era of AI-powered edge devices, automotive electronics, and other demanding applications. But rather than manufacturing the chips ourselves, we license our technology to companies that integrate it into their own semiconductor products.

This approach is known as semiconductor intellectual property (IP) licensing model, a model that is well established among global semiconductor leaders such as Arm and Ceva. If you don’t know about this model, it’s worth understanding why this model is so compelling.

Asset-light, high-margin, and scalable

Traditional chip manufacturing requires enormous capital investment in fabrication plants (“fabs”) and equipment. Advanced fabs today cost tens of billions of dollars to set up. In contrast, an IP licensing company like Weebit focuses on developing and perfecting its technology. It then licenses it to customers who either have their own manufacturing capabilities or use foundries to outsource manufacturing of their designs.

Weebit provides two types of licenses: manufacturing and design. A manufacturing license gives a fab the right to manufacture devices which include our technology, and a design license allows a product company to embed our technology into their chip.

In the case of a manufacturing license, the customer will also pay a Non-Recurring Engineering (NRE) fee to cover the cost of the technology transfer and qualification. In the case of a design license, the customer might ask for some modifications to the memory module, in which case they will pay NRE fees on top of the design license fees. Once their chips go into mass production, Weebit will receive a royalty payment for every chip sold that uses our technology.

Above: The IP business model can look slightly different, depending on the type of
company we are licensing to (e.g., a foundry, IDM, or product company).

Because we don’t need to build factories or maintain inventory, our operating costs are relatively low, and our gross margins can be very high. Looking at comparable IP businesses, such margins can often exceed 90%. This means that once royalty streams begin, revenues can scale quickly without a corresponding rise in expenses.

Long-term, sticky revenues

Another strength of the IP licensing model is its staying power. Once our technology is embedded in a customer’s chip design and manufacturing process, it tends to remain there for the lifetime of that product. For Weebit, that can mean many years of recurring royalty payments from a single design win.

The result is a growing base of long-term, high-margin revenue streams that can compound over time as we add more customers and applications.

Global market opportunity

The global semiconductor market is vast, and with flash memory reaching its scaling limits, there is a growing need for next-generation embedded memory technologies like ReRAM. While some companies develop and use their own ReRAM internally, the majority of the market is open to external licensing. That’s the opportunity Weebit is targeting.

We’ve already signed initial license agreements with major players including DB HiTek (a foundry) and onsemi (an IDM), and we’ve recently signed our license to an end product company in the U.S. We are working towards additional agreements with other such companies across key sectors.

You can read my earlier article, World IP Day: A Time to Reflect on the Value of Semiconductor IP, to learn more about the different types of semiconductor IP and how such solutions are delivered. You can also read more about Weebit’s technology, market position, and licensing strategy in this recent article where Andrew Johnston, Industrial Analyst from MST Access, explores why the IP model is such a powerful driver for our ReRAM ambitions: How Weebit Nano’s IP strategy is fuelling ReRAM ambitions.

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Low-power design is critical, especially for chips inside battery-operated IoT devices that must support applications for several years on one battery in a very small area. Embedded non-volatile memory (NVM) for these devices must have ultra-low-power, high endurance and high reliability to support continuous monitoring, logging and communicating of small amounts of data over the product’s lifetime.

Ultra-low-power embedded NVM like Weebit ReRAM (RRAM) can enable longer use times between recharges or battery replacements and help improve system energy efficiency. The low voltage levels used for memory transactions, coupled with ReRAM’s fast memory access time, greatly reduce power consumption. And with programming, standby, sleep, and very deep power-down ReRAM modes, as well as rapid wake-up from deep power-down, designers can enable near-zero leakage power of internal and external NVM. You can read more about this in my previous article, ‘How Low Can You Go? An Inside Look at Weebit ReRAM Power Consumption’.

By reducing power consumption, the memory subsystem can also allocate more power to other critical components to enhance overall system performance. Designers can take this advantage even further by implementing smart, power-aware system memory partitioning strategies. This includes dividing data intelligently across volatile and non-volatile memory resources to reduce the size of system SRAM.

Smart memory partitioning in practice

In a wearable sensor designed to monitor a specific health parameter, it is common to store code on external flash and then load code onto the local code SRAM from which the MCU then fetches the code. Each time the system wakes up to log and process data, there is MCU power consumption related to executing the Write cycles; as well as time and energy needed to load the code from the external flash into the code SRAM, and for the MCU to fetch the code. There is also power required to maintain the code SRAM or keep on the always-on logic for these operations.

Above: Typical MCU architecture with external flash

An alternative way to architect this would be using an eXecute in Place (XiP) architecture where on-chip ReRAM can be used to store code instead of the code SRAM, and the MCU can fetch the code directly from the ReRAM. This reduces system wake-up time and decreases power since there is no need to access the external flash. It is also possible to turn off the code ReRAM to further reduce power. Our calculations show that this can result in 30% power savings over the previously described traditional architecture.

In addition, instead of storing log data to external flash, we can store it into on-chip ReRAM, eliminating the external flash altogether. If we replace the on-chip code SRAM as well as part of the data SRAM with ReRAM, we can achieve a total of 60% power reduction, and a device that can last up to four years!

Finally, instead of logging the data into SRAM and storing processed data onto ReRAM, we can log processed data directly into ReRAM, thereby eliminating most of the on-chip SRAM. In this way we can reach a total of more than five years of lifetime for this application. With NVM like ReRAM, there is close to zero power consumption needed to retain the data during inactive states.

Above: Example medical device logging system with on-chip ReRAM for code and data

Enabling new use cases

Reconsidering the memory technology and architecture in a typical IoT sensor/medical logging device can enable advantages in terms of power consumption and device lifetime. This becomes even more important with a device that doesn’t have a battery. In a device using energy harvesting, a traditional architecture can be prohibitive. Using a combination of logging data in SRAM and uploading it to flash can actually consume more power than what’s available!

Advanced hearing aids, wireless earphones, pacemakers and other medical and wearable appliances that need over-the-air (OTA) firmware updates can also benefit. In our calculations, performing a chip erase and then programming the new code required for the OTA update requires more time and energy than what is available using a standard off-the-shelf ultra-low-power flash device.

Embedded NVM like ReRAM, coupled with smart memory partitioning, can improve the energy efficiency of battery operated and energy-harvesting ICs. In a new article in Electronics Weekly, I go into greater detail on the different architectures and power savings that can be achieved.

Read the full article here.

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