When it comes to cars, safety and reliability are paramount. That’s why almost every single part of a car must meet standards and regulations designed for the specific stresses the component could face throughout its lifetime. This includes everything from engine components to the infotainment cluster to the window glass. Pretty much the only standard parts of a car that aren’t subject to such controls are the cup holders.

The strictest standards are those for safety-critical components like brakes, seatbelts and airbags, tires, steering systems, and engine control and monitoring. These systems must comply with multiple regulatory and industry standards – including passing crash and durability tests as well as compliance checks – because they directly impact passenger safety.

When it comes to vehicle electronics, there are similar strict reliability tests, especially with the increasing complexity and proliferation of technologies like advanced driver assistance systems (ADAS). For integrated circuits (ICs) including microcontrollers (MCUs), sensors and memory chips, the qualification standard is called AEC-Q100.

AEC-Q100 is a stress test qualification established by the Automotive Electronics Council (AEC), an organization originally formed by Chrysler, Ford, and GM to establish common part qualification and system quality standards. The council provides an official document that outlines the AEC-Q100 qualification process called Stress Test for Qualification for Integrated Circuits.

If a device is qualified to AEC-Q100, it means that it has passed the specified stress tests and guarantees a certain level of quality/reliability. This makes AEC-Q100 qualification important not only for automotive applications; knowing a technology is AEC-Q100 qualified tells designers of all applications that it is very high quality, so they can feel more confident when using it.

Withstanding Harsh Conditions

AEC-Q100 defines four ambient temperature ranges (known as ‘grades’) designed to cover the several different thermal environments in which automotive applications operate. This classification enables designers to select the components that align best with their needs. The lower the grade; the more qualification constraints are required. AEC-Q100 defines four ambient operating temperature ranges:

• Grade 0: -40°C to +150°C
• Grade 1: -40°C to +125°C
• Grade 2: -40°C to +105°C
• Grade 3: -40°C to +85°C

Grade 0 components are rated for extreme conditions and can handle the harshest environments in a vehicle. This includes devices used in powertrain and engine control, and many others that must be able to withstand high temperatures, vibration, and continuous operation.

Beyond the ability to reliably withstand harsh conditions, automotive ICs must also be designed for safety, security and longevity. Some requirements can be quite different than those in consumer markets.

Above: consumer versus automotive requirements

Non-Volatile Memory in Automotive

Non-volatile memory (NVM) for automotive must support fast boot, instant response, and frequent over-the-air (OTA) updates. Increasingly, auto makers are looking to integrate an MCU and embedded NVM in a BCD process to replace solutions that previously used an external standalone memory. And, as many SoCs move to advanced nodes to meet performance requirements, companies are looking to alternatives to embedded flash like Weebit ReRAM.

ReRAM (RRAM) is reliable at high temperatures, it can withstand harsh conditions like vibration and electromagnetic interference (EMI), and it has high endurance, fast switching speed, long-life, and innate security. It can also effectively scale to the most advanced process nodes.

When supplying NVM for automotive applications, it must achieve AEC-Q100 qualification.

Accelerated Stress Testing

To achieve AEC-Q100 qualification, it’s necessary to test three unique lots which ran at different times in the production line, with 77 samples per lot to assure the statistical significance level for very low failure rates. The samples must undergo 1,000-2000 hours of accelerated testing with zero failures – for each of the specified tests. For a discussion of accelerated testing, see our previous article, “Compressing a Lifetime’s Worth of Stress: ReRAM Qualification Explained.”

Tests include those for endurance, data retention, and operating life. To rate for Grade 0 applications, the samples must repeatedly demonstrate 150°C operation for up to 100K endurance cycles, with very low bit error rate (BER) throughout. The specific flow and tests are outlined in the AEC-Q100 Rev D1 Non-Volatile Memory Program/Erase Endurance, Data Retention and Operating Life Test.

Looking beyond the baseline stress tests, there are also specific mission profiles that we must consider.  The qualification flow mentioned above gives a great deal of confidence to potential customers, however, when selecting a part for their specific applications, companies must look at the specific use case surrounding a part.

A part may be expected to reach the highest temp of 175⁰C for only 0.02% of the time and -40⁰C only 4.20% of the time, but for most of the time, the part operates at much more moderate temperatures. See an example of such a mission profile in the table below.

Commonly, companies put together sets of numbers that estimate the percentage of time a part will be at a certain temperature, then calculate the numbers to determine whether the expected real-life stress is expected to be less than or more than the stress that was applied during qualification. If the result is less than the qualified time, customers can be confident the part will not fail from aging issues during its normal lifetime.

Above: An example of a calculation for an automotive mission profile

Conclusion

Having an embedded NVM module that is fully qualified for AEC-Q100 is the first big step to getting the NVM designed into automotive applications – as well as other applications in harsh environmental conditions. Automotive end products that use devices in a new process must be qualified for AEC-Q100. Each time a module incorporating a specific technology like Weebit ReRAM is qualified, it demonstrates that the technology is mature, it is thermally stable with high endurance, and it reaches the standard of zero defects per million parts.

In assuring quality in each part of the vehicle, every single player in the supply chain must ensure their part adheres to quality standards. From IP makers like Weebit to semiconductor companies, product companies, foundries, systems companies and automakers – and others in between – functional safety is a clear priority. At Weebit we are dedicated to ensuring our IP is proven ready for integration in automotive applications today.

AEC-Q100 qualification is a sign of high quality, not only for automotive, but for all application domains.

Want to learn more about the potential of Weebit ReRAM in automotive?
Check out this recent article in EE Times, which touches on the topic: Onsemi’s Treo Taps Weebit ReRAM.

The post The Road to AEC-Q100 Qualification appeared first on Weebit.

Awhile back, I wrote an article describing the concept of technology transfer, explaining that when a fab gets ready to start manufacturing a new technology, it must work closely with the technology developer to create the perfect recipe – including the materials, process, tools and equipment, and other variables.

In this article, I would like to focus specifically on the materials piece of that recipe. I’ll explain what ‘materials’ are in the context of semiconductor manufacturing and explore what we mean at Weebit Nano when we talk about our use of ‘fab-friendly materials’ as an advantage of Weebit ReRAM.

Let’s define ‘materials’

‘Materials’, according to the Merrian Webster dictionary, are “the elements, constituents, or substances of which something is composed or can be made.”

Manufacturing most goods today includes myriad materials that are used in a complicated chains of processing steps. Take leather goods for instance. There is a broad set of materials needed to process the finished leather, before it becomes ready to be made into end products like shoes and bags. Materials include those that comprise the end products, such as the hides themselves, as well as dyes, waxes and oils. There is an even broader mix of materials that are used in the fabrication process and then thrown away, such as cleaning agents, preservation and tanning materials and finishing agents.

Similarly, when we talk about semiconductors, we are talking not only about the materials that comprise the actual semiconductors themselves (in the stack and interfaces), but also about the substances that are used in the fabrication/manufacturing of the wafers and then disposed of.

Some materials are uniformly applied, while others are applied in patterns. In leather goods, this is done through techniques such as embossing and engraving using predefined texture plates. In semiconductors, many materials are applied using photomasks through which the materials are deposited on specific areas of the wafer.

Materials used in semiconductor manufacturing

Some materials like copper and aluminum are very good conductors of electricity, and others like rubber and wood have insulating properties and therefore prevent conductivity. Semiconductor materials have properties of both conductors and insulators, enabling conductivity under certain controllable conditions like temperature, pressure, and other process parameters. These materials are critical to electronic devices, enabling control of the electricity flow.

According to the IEEE, the most widely used semiconductor materials are silicon (Si), germanium (Ge), and gallium arsenide (GaAs). Germanium was used early on and is still used for some applications, but silicon, which is the second most abundant element in the earth’s crust, has been used extensively in semiconductors since the 1950s.

Silicon is efficient and economical to extract, purify and crystallize, and it’s straightforward to mass-produce. Within standard CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing flows, silicon or compounds of silicon are the most widely used. Since pure silicon is more of an insulator than a conductor, a process called ‘doping’ is used to add tiny impurities (atoms of other materials) to the silicon to make it more conductive.

There are also materials used in manufacturing that are built into the stack for metal layers, interconnects, conductive barriers, and so on. Then there are the materials that are disposed of after use. Like the cleaning, curing and tanning agents we need to process leather, these materials – including gases, solvents, polymers, and others – are not actually part of the end products, but they are needed for processing.

Above: an example CMOS process courtesy of https://www.scl.gov.in/cmos.html

“Friendly” versus “unfriendly” materials

Choices of materials are often based on their inherent electrical properties, changes under different environmental conditions, interactions with other materials, and their compatibility with existing CMOS technologies.

This latter consideration is something we refer to at Weebit as being ‘fab friendly’ and it’s a differentiator for our ReRAM (RRAM).

An article written awhile back by my colleague, Eran Briman details an environmental initiative we completed with our R&D partner CEA-Leti which clearly shows the difference between friendly and unfriendly materials. The initiative compared Weebit ReRAM to MRAM technology, and results showed that the environmental impact of ReRAM is much lower than that of MRAM. Read Eran’s article to learn more about the criticality of various materials used in semiconductor manufacturing, and why the materials used in Weebit ReRAM are much friendlier than those used in MRAM.

Unfriendly materials

Critical and rare earth materials are very expensive often due to the cost of their extraction. Their extraction is also often very unfriendly to the environment, and their use can be complicated by political factors. Rare earth materials can add huge costs and complexities to the manufacturing process, so minimizing their use is very important.

Some materials aren’t rare earth materials, but they still aren’t very friendly – whether to the environment, or to adoption by a fab. Using more exotic materials can require additional dedicated clean room space, vacuum technology, extra tooling, standalone etch and deposition tools, special cleaning protocols, different wafer handling processes, and myriad other considerations. There can also be added issues with equipment degradation, sewage and recycling requirements.

Materials like iron (Fe) and Nickel (Ni) are considered unfriendly to CMOS fabrication, so strict protocols are followed to prevent contamination from these metals. Even trace amounts can lead to significant reductions in performance, stability, and reliability, so their use requires specialized equipment and cleanroom conditions to maintain the purity and performance of the devices.

Another example is PZT (a combination of lead zirconate (PbZrO₃) and lead titanate (PbTiO₃), which is used in medical imaging equipment, sensors and actuators, energy harvesting systems and FeRAM (Ferroelectric Random Access Memory). But in a CMOS fab, PZT is unwanted because of the lead contamination risk, material compatibility issues, additional process complexity, and reliability concerns associated with ferroelectric materials. In modern CMOS fabs which aim to minimize contamination risks and simplify the manufacturing process, PZT is typically avoided in favor of more compatible and environmentally friendly alternatives for applications requiring piezoelectric or ferroelectric properties.

Fab-friendly ReRAM

The materials used for creating our ReRAM are already used as standard in CMOS flows. Such materials compatibility makes it easier for companies to adopt our ReRAM, as they already know how to deal with these materials, and normally already have the tools needed to work with them. This enables them to avoid high cost and potential issues with reliability or cross-contamination with other materials in their flow.

Since fabs are such delicate environments with extremely sensitive (and very expensive) tools, any change can be very costly and have significant impacts. Introducing “unfriendly” materials which are not commonly used in the fab (or not used at all), requires a deep understanding of them and how they impact the environment in the fab. It often requires new processing tools t and new manufacturing procedures. But most of all, these materials have the potential to contaminate the environment. All these reasons make such materials difficult to adopt and become a major hurdle for new technologies using them. This is a key reason for the failure of some of the competing ReRAM technologies.

The ‘Secret Sauce’ of Materials

The many components and pieces of IP within a semiconductor chip can be comprised of different materials.

For ReRAM, different types of metal oxides can be used as resistive materials, with choices made based on electrical performance and compatibility with existing CMOS technology. There are also inert metals added on the top and bottom electrode layers which are chosen for various technical reasons.

As a developer of ReRAM IP, there are many materials that we can select from that provide the performance needed within a standard CMOS flow. We’ve chosen those that are the fab-friendliest. And it’s not just about the specific materials themselves; we are able to combine materials under different conditions to achieve the best possible performance. This is enabled by the expertise of our Device and Process teams, including more than a dozen PhDs in Physics and Chemistry.

It’s also about the process itself. Manufacturing Weebit ReRAM adds two masks to the manufacturing flow, versus up to 10 added masks for flash. Choosing ReRAM translates to fewer layers, less waste, and a more environmentally friendly process. On top of this inherent advantage, the Weebit Process team focuses on how to manufacture the cell efficiently in different fabs and different process nodes.

As customers look to choose the right embedded NVM for their SoC, there are many factors that can affect their decision. When it comes to materials, choosing Weebit ReRAM is the friendliest option – from a cost, complexity and environmental perspective. When combined with our performance and reliability advantages, the decision is clear!

The post Living in a (Semiconductor) Material World appeared first on Weebit.

When DB HiTek licensed Weebit ReRAM, we mentioned that the ReRAM (RRAM) will be implemented in their 130nm Bipolar-CMOS-DMOS (BCD) process. We also mentioned that a BCD process is ideal for mixed-signal and high-voltage designs in applications such as consumer, industrial, automotive and IoT devices.

But what is a BCD process, and why is it a good fit for these applications?

A quick look at the Swiss Army knife

Perhaps the best way to start talking about BCD is with an analogy. So, let’s take a quick look at the Swiss Army knife! This well-known tool was conceived in the late 1880s, when the Swiss Army decided to provide soldiers with a folding implement that would enable them to open cans of food and disassemble their service rifles – which needed a screwdriver. Thus, the Swiss Army knife – the first folding pocket multi-tool – was born. It combined three functions into one valuable tool that would make the lives of soldiers much easier.

In 1896, Karl Elsener redesigned the knife around a spring mechanism that enabled tools to attach to both sides of the handle, making it possible to increase the number of tools on the knife. Since that time, the Swiss Army knife has evolved to include many other tools, but the original premise remains, and recruits in the Swiss Army still receive a knife when they join up. You can read more about the history of Swiss Army knife on the Alpenwild travel site.

Above: A typical Swiss army knife integrating various tools in one platform

BCD: A hybrid process for power management applications

Like the Swiss Army knife, BCD is a multifaceted platform with versatile characteristics. BCD was originally built as a hybrid technology platform based on advances in several areas over several decades, and it continues to evolve today.

After the introduction of integrated circuits (ICs) in the 1950s, various substrate technologies emerged, starting with Bipolar analog focused processes in the 1950s. In the 1960s, we saw the introduction of Complementary Metal-Oxide-Semiconductors (CMOS) for digital processing. In the 1970s, Double-diffused Metal-Oxide-Semiconductors (DMOS) transistors were introduced for power functions and high voltage elements.

Throughout this time, end products and their analog and digital components continued to grow in complexity, often with different voltage and power requirements within the same product. Processors, communication, and other digital ICs focused on CMOS substrates, while analog focused on Bipolar, and power designs were more likely to use DMOS. However, over time, the need to have a mixture of these in the same design grew, presenting a challenge in integrating mixed-signal and high-voltage designs on a single die.

In 1985, the manufacturer SGS (now STMicroelectronics) introduced BCD (Bipolar-CMOS-DMOS) technology which combines Bipolar, CMOS, and DMOS technologies all in one. BCD makes it possible to combine three different types of transistors – analog, digital and power/high voltage– all on the same silicon die, leveraging the strengths of each type of transistor. The result is the ability to design and fabricate a chip that can handle various voltage requirements and power levels.

Each of the technologies in BCD provides distinct advantages. For example, DMOS makes it possible to accommodate a wide range of voltages, so it can be used for high-voltage or low-power applications. The inclusion of CMOS enables designers to integrate digital blocks while optimizing power efficiency. With Bipolar transistors, a design can manage large currents for power-intensive use cases.

There are also benefits based on the combination. This includes enabling higher integration density for end solutions with a more compact footprint. This is like the Swiss Army knife, which puts multiple functions into one tiny instrument that fits in your pocket! System integration also enables solutions with greater energy efficiency, improved system reliability, and reduced electromagnetic interference (EMI).

Where does BCD make a difference?

Because it enables integration of analog components, power transistors, and digital logic in one chip, the applications for BCD technology are broad. It is most applicable where there is a need for power efficiency, thermal stability and high-voltage capabilities. BCD is also used where it makes sense to integrate various components on a single chip.

Applications include power management ICs (PMICs) where it helps reduce standby power and increase efficiency and system reliability. Many of today’s power management units use smart PMIC designs where the PMIC is integrated with a microcontroller (MCU) on one die. This enables them, for example, to optimize the charging speed based on the state of the battery, extending battery life. You can read more about this in our article, “The Power of ReRAM for PMICs.” For PMICs, BCD leads to performance, security, power and cost advantages.

Other key applications include motor control in industrial automation and robotics, display driver ICs and wireless charging. It is also essential in automotive applications, especially where analog (motor control) and power management (for smart charging) are integrated in areas such as body electronics (e.g., lighting, power windows, door locks, mirrors, windshield wipers, etc.), powertrain control, and electric vehicles.

Since the 1980s, ST and many other industry players have continued to develop techniques to make BCD processes more effective alongside advancements in end products, manufacturing techniques and process nodes. Because of its broad applicability, developments have continued to maximize separately for high power, high density and high voltage. This work continues, and today many major foundries and IDMs offer their own flavors of BCD.

NVM for BCD

Non-Volatile Memory (NVM) is broadly used in many BCD and high-voltage designs. At the minimum, such NVM is used to store calibration and trimming information, on top of some ID/security data. More recently, as we see BCD designs integrating further resources onto a single die, such NVM can be used also for code storage – especially for designs that integrate a microcontroller. This enables cost-effective support for updates in the field, secure data storage, and diagnostic capabilities, which enhance the flexibility, reliability, and safety of such devices.

A high-quality BCD process requires precise calibration of the front-end-of-line (FEOL) in the manufacturing process, which is very sensitive to variations. Typical NVMs like flash are integrated in the FEOL, making their integration into a BCD flow very difficult and costly. In addition, this impacts the design’s transistors which must take NVM integration into account, making the design less than optimal. Think about integrating new tools into the Swiss Army knife. Depending on their size and shape, everything in the knife may need to be shifted around to make room for the new tools (this is why there are today more than 100 versions of the knife!).

Weebit ReRAM offers significant advantages because it is a back-end-of-line (BEOL) technology which doesn’t require any process tuning and doesn’t impact the transistors in the front-end-of-line. Like the toothpick in the Swiss Army knife – it doesn’t influence the other parts of the knife. ReRAM also requires fewer masks than flash, making it less complex and cheaper to manufacture.

Many companies designing power management and high-voltage designs are looking to enjoy the advantages of embedded ReRAM – including low cost, low power, easy integration, and proven excellent retention at high temperatures. At Weebit, we’re working with foundries like DB HiTek to make our ReRAM IP available in their portfolios. We recently taped-out our module in DB HiTek’s 130nm BCD process.

And while we can’t open our customers’ cans and bottles for them, we can make their lives easier by providing a low-power, cost-effective and high-density NVM that can help them save cost and power and reduce the complexity and size of their solutions.

The post Integration and Flexibility:<br>A Brief Introduction to BCD Process Technology appeared first on Weebit.

I’ve been thinking a lot lately about the concept of endurance in my preparation for a half marathon in the Dead Sea race, and also as I start training towards my first full marathon of 42.195 kilometers three months from now. To run such long distances, high endurance is one of the most important things to focus on. Of course, it helps if you start with the right physical attributes for distance running, but that is definitely not enough. High persistence, strength and resistance training are key factors for increasing endurance.

Endurance is also one of the most important parameters for memory technology. As memory developers, one of Weebit’s key priorities is ensuring high endurance, balanced with other critical factors such as data retention.

The importance of endurance and retention

The Non-Volatile Memory (NVM) inside a system is responsible for reliably and securely storing firmware and important data such as operating system files, application data and user data. Not only must the NVM retain that data for a system’s lifetime; it must maintain consistent performance levels to ensure that applications continue to run smoothly. This means that high endurance and data retention are critical. Devices with higher endurance can serve and be used for broader use cases and applications.

Data retention

As you probably know from our previous posts, NVMs like ReRAM (RRAM) can retain data even when powered off. This is step one when it comes to data retention! Beyond that, when we talk about a memory’s data retention time, we refer to how long stored data can be saved on the device at a specified temperature. The retention of most NVM devices is measured at 10 years @ 85⁰C.

While most NVM technologies can’t normally achieve such retention at higher temperatures, Weebit ReRAM can retain data reliably at high temperatures for longer than required, making our ReRAM a great fit for a broad range of industrial and other applications.

Endurance in non-volatile memories

In NVM technologies, endurance is a measure of how many times data can be reliably written and rewritten to the memory cells before the device wears out or becomes unreliable. NVM devices must reliably retain data and code for long periods of time; however, as data is written/erased/re-written, the storage medium experiences degradation over time. This is because each voltage assertion change in the memory state from positive to negative or negative to positive leads to atomic-level microscopic changes that gradually accumulate. This is true for all memory technologies. Depending on the application, the memory cells may need frequent updates, so it’s important to select a memory that is designed for suitable number of write cycles, referred to as “endurance,” from the outset.

Endurance varies significantly between different memory types. SRAM and DRAM have practically unlimited endurance, but they are volatile, meaning they lose their data once the power is turned off. In non-volatile memories like flash or ReRAM, endurance is much more limited, and the key is to provide the requisite amount of endurance for most applications.

Looking at NVMs, Weebit ReRAM typically has significantly better endurance than flash memory and is expected to achieve between 100,000 and a million write cycles versus the typical 1,000-10,000 program/erase cycles that flash can handle. This makes Weebit ReRAM a great fit for applications that require frequent memory updates such as automotive, security and data logging.

Above: ReRAM typically has higher endurance than other NVMs

One of the reasons that ReRAM has higher endurance than flash is that we do not need to erase data before writing new data in the memory cells. With flash, old data must be erased before it is replaced with new data, so every write operation is actually two writes. With ReRAM, data can simply be overwritten, causing less degradation to the memory.

In addition, since Weebit ReRAM is bit addressable, we write only to the needed bits for any operation, unlike flash which must access entire sectors of data every time it erases or writes. Last, but not least, flash uses high voltages for programming, adding to faster degradation of the material due to the increased voltage stress limiting its endurance.

Finding a balance of electrical voltage and current

While higher applied voltage decreases the endurance of a memory, higher electrical current actually leads to better retention in ReRAM devices. ReRAM works by applying different voltage levels on the resistive layer, enabling the creation or dissolution of a filament. This filament becomes thicker with a stronger electrical current. This means it can withstand more time and heat. So for ReRAM, the stronger the current, the better the data retention.

Balancing between the set (writing a ‘1’) and reset (writing a ‘0’), voltage and programming current are therefore key. Every time we characterize new silicon, part of the process is to test the device by altering the different parameters to ensure the ideal balance.

RESET (Erase) Partial dissolution of the Conductive Filament: LRS >> HRS

SET (Program) – Recreation of the Conductive Filament: HRS >> LRS

We also use smart algorithms to tune the writing parameters for a design to ensure an ideal balance for a specific application. There are many different voltages that can be used for Set and Reset, and a similarly wide range of pulse width, limitation and termination settings, as well as other variables. By independently tuning these variables, we can enable the best possible combinations for a target application. You can read more about Weebit’s smart algorithms in the blog article, “ReRAM Gets a Boost from Smart Algorithms.”

The impact of environment

As with the human body as it prepares for a marathon, having the right physical foundation is key to good endurance. But the environment can play a huge role in performance as well. Obviously, running for 42.195Km (26.2 miles) will be difficult no matter where you run. As runners, we must prepare for every weather condition since on the day of the race it can be cold, it may be hot, rainy or sunny, sometimes even hailing, and each condition presents a different set of challenges. The heat, cold, elevation and other conditions will test even the most experienced runners.

Electronic devices are also affected by the environment, since all semiconductor devices depend on physics and chemistry. You may have heard lately how the extreme cold weather in the U.S. has been shown to shorten the range of Tesla vehicles. This is because the lithium ions inside EV batteries flow more slowly when it gets cold and do not release as much energy. For every memory technology, higher temperatures have a negative impact on endurance. This reaction is exponential, so that as the temperature elevates, even a few degrees can pose a challenge.

As I’ve already mentioned, most NVM devices are qualified at 85⁰C, and our Weebit ReRAM module is already fully qualified at temperatures of up to 125⁰C, and we will be working on qualifying at higher temperatures in the future. Based on physics, ReRAM is inherently more stable at higher temperatures than other NVMs.

Increasing endurance

One of our main ongoing goals is to increase the endurance and retention of our memory. For example, moving from 1,000 cycles to 10,000 cycles to 100,000 cycles and beyond. How do we do this?

For a 100-meter race, you might advise someone to start fast and just continue to push faster. But this is definitely not the best advice for long range marathon, or even 10 kilometers, since obviously you will soon wear out and collapse. In addition, each stride causes stress on our knees and can cause microscopic ruptures in our muscles, so it’s critical to train gradually to avoid injuries. This is also true for a memory device while trying to increase your endurance towards 100K write cycles. We must maintain our strength by not pushing the limits. This way, we can extend the wear-out level.

In other words, we try to reduce the stress on the memory as much as we can and keep it in good shape throughout its entire operation process, giving it a little boost only when needed.

As I continue to train for my next race, I am focused on increasing my own endurance. I do that by training and running at least 3-4 times/week and increasing the distances that I run during the weekend. In addition, I must increase muscle strength by lift training at the fitness center, maintain a healthy diet, and get sufficient sleep to enable my body to recover and build muscle mass.

This way, I will soon work my way up to a full marathon in the next few months side-by-side with Weebit as we continue to increase the performance of Weebit ReRAM.

Above: A picture of the author completing the half marathon (21.1Km) in the recent Dead Sea race

Note: All qualification data is based on well-known JEDEC industry standards for NVMs.

The post Marathon Running:<br>Memory Endurance<br>and Retention Explained appeared first on Weebit.

One of the key advantages of Weebit ReRAM (RRAM) is the technology’s ultra-low power consumption. Some of this advantage is due to the inherent features of the technology, and some of it is due to smart design. In this article we’ll explain why customers need a low power non-volatile memory (NVM) and what makes Weebit ReRAM lower power than other types of NVM. We’ll also explain a bit about some of the design techniques and levers that customers can use to adjust the power.

Why is low power consumption important?
In our rapidly warming climate, it has become critical to minimize carbon emissions, and this includes reducing the power consumption of everything we touch – from our homes to our cars to our personal electronic devices and beyond. This is now a key consideration at the government level in many countries, and is a key consideration for institutional investors.

At the practical level, for companies developing electronic products, low power consumption is often a key consideration, especially when it comes to battery operated IoT devices with Bluetooth® Low Energy or energy harvesting technology, and medical devices such as wearables and implantables.

Such devices must ensure that data gathered by tiny sensors is regularly and reliably delivered, often from remote or inaccessible locations. For many of these applications, whether in medical, transportation, agriculture, or other applications, reliability can have life or death consequences. Long battery life – supporting applications that last up to 10-15 years on one battery – is critical.

Above: Various ultra-low power attributes of Weebit ReRAM lead to longer device battery life.

Even for products that are plugged into power, designing for low power can be an important consideration. Developers want to avoid costly fans and heat sinks, reduce overall electricity costs, and meet consumer product energy efficiency standards including certifications like Energy Star and LEED for products and buildings, as well as EU energy efficiency labeling. Such guidelines consider not only active power consumption, but also ‘leakage’ power consumed when a product is not in use.

The Role of NVM in Reducing Power Consumption
While NVM may not contribute as much to system power consumption as other components such as the CPU, connectivity modules or display, reducing its impact is a key goal for an overall power management strategy.

As part of a system, choosing ultra-low-power NVM helps to enable longer battery life, leading to improved energy efficiency and longer use times between recharges or battery replacements. It can also lead to better thermal management and overall greener technology. Importantly, by reducing power consumption, the memory subsystem can allocate more power to other critical components, such as the processor or display, improving overall system performance.

When it comes to NVM, there are various factors that contribute to power consumption, such as the power consumed by Read and Write operations, standby power, access frequency and overall system design. Let’s look at some of these in a bit more depth.

Read Power Consumption
In an NVM ‘Read’ operation, data is retrieved from a specific memory location. This includes decoding the address to identify the specific memory location to be accessed, retrieving the data, and outputting the data for processing elsewhere in the system. The ‘Read’ operation is the most common NVM operation, happening many more times than programming the cells, and thus consuming more power.
The power consumed during a Read operation depends on several key factors. One of these is the power supply used. Flash and some other types of memory require a special high voltage supply. Weebit ReRAM is able to read out of a low-voltage power supply – the same one that any system needs for basic calculations. With Weebit ReRAM, there is also no need for an always-on charge-pump – something that is needed with flash memory.

Another contributing factor is cell reading voltage and current. The cell reading voltage refers to the voltage level applied to a memory cell during the read operation. Different memory technologies have specific voltage requirements for reading data from their cells, and these can vary based on the specific memory technology, fabrication process, and design considerations. With Weebit ReRAM, a Read operation is performed using only the digital core voltage (VDD), and the Read cell voltage for ReRAM is typically a few hundreds of millivolts (mV) or lower.
The typical Read cell voltage requirements for other NVMs are higher, typically in the range of 1 to 3V for flash, and several hundred mV to a few volts for MRAM. Weebit ReRAM also has a dedicated “read-only-mode” during which program voltage can be completely shut-off.

These are just a few considerations in terms of Read power consumption. Other important things that impact Read power include:

• The number of data bits read in parallel, including error correction code (ECC) bits: Weebit’s ReRAM architecture is flexible to support different word widths based on the system architect’s preference.
• Memory array capacitance: In Weebit ReRAM, the bitline capacitance is reduced due to array segmentation.
• Sense-amplifier efficiency: Weebit’s engineers have innovated and optimized the sensing circuitry to consume extremely low power per bit.
• Control logic and self-timing circuitry: Weebit ReRAM has a single-ended Read operation with self-timing to enable the operation to terminate as soon as it is complete.

Fast Read times in Weebit ReRAM also allow Execute-In-Place (XiP) to further save system power. We will cover this in a future article.

Write (Program) Power Consumption
In an NVM Write operation, data or instructions are stored or updated to a specific location. This is a complex operation encompassing many events which, of course, consume power. Power consumed during programming is mainly dependent on:

• The number of data bits to be programmed
• The power supply used during SET and RESET operations
• The current through the cell during the SET/RESET operation
• The write circuitry (LDO, limitation, termination) efficiency
• The ability to shut off the power as soon as the operation has completed

In terms of the number of data bits to be programmed, one of the key advantages that ReRAM and other emerging NVMs have over flash memory is that these technologies do not require a sector erase. With flash, even if you just want to erase one bit, you actually must erase the entire sector or segment, and before erasing that sector, you first have to program all the new bits including those that didn’t even need to be programmed. This is obviously a lot of extra work and power. Designers working with flash have found ways to work around the challenge and mitigate the penalties associated with the extra programming and erasing, but even with these workarounds, emerging memories like ReRAM are significantly more power efficient.

With ReRAM, using its direct program/erase capability and byte addressability, the programming is bit-wise: each bit can be independently and selectively SET or RESET. Importantly, with Weebit ReRAM, a programming algorithm does a comparison to existing data to avoid unnecessary writes and then masks out the bits that do not need to be reset.

Above: A programming algorithm compares new data to existing data and only resets the new bits.

The programming algorithm also splits Words into Sub-Words to control peak power consumption to mitigate against any issues such as IR-drop or power supply failure. Weebit ReRAM implements smart programming algorithms that control voltage, current and pulse duration during the Write operation, enabling efficient usage of resources.

Flash memory often requires high voltages for programming, sometimes requiring voltages generated by a charge pump or DC-DC converter. These types of converters add area to chip, add cost to the system and waste power. With Weebit ReRAM, programming is ultra-low-power, capable of being done using a lithium cell battery. It also requires low voltages (using a ~3V supply) with no charge pump needed when a ~3V IO voltage is available.

As with a Weebit ReRAM Read operation, Smart algorithms enable the shortest possible Write time and a termination mechanism shuts off the programming pulse as soon as the cell is flipped.

Standby/Sleep/Power-Down Modes
Depending on their specific application and operation, a key design consideration for customers is how often the memory can be in programming mode, standby mode, sleep mode, or very deep power-down mode.
During the inactive states of the system, there is significant cell leakage when using a volatile memory such as SRAM. Similarly with DRAM there are “hidden” refresh cycles that consume power during these states. With any non-volatile memory, there is close to zero power consumption used for retaining the data during inactive states. Like other NVMs, Weebit ReRAM is able to be completely powered down to zero leakage while maintaining stored data. The fact that ReRAM does not require an always-on charge pump makes this advantage even more evident.

The wake-up time of a memory from deep power-down mode to active is also a key factor. A memory that can wake up rapidly from power-down mode to read (or programming) mode allows the system architect to put the memory to sleep even during shorter activity breaks. Said another way, waking up quickly means the system can also go to sleep more often. Again, not having a charge-pump makes this advantage even more meaningful as charge-pumps are known for their slow and power-hungry wake-up times.

Weebit engineers are focused on continuing to reduce the time needed for our ReRAM to wake up from very deep power-down mode. The time is already very fast to switch from power-down to standby mode, and we are in the process of further reducing this by orders of magnitude.

We are focused on providing customers with flexibility when it comes to their choices. One of the benefits of working with Weebit is that our designers are experts at optimizing these parameters and we are willing and able to work with customers to help them optimize their designs to balance performance and power consumption as well as other parameters. If you’d like to learn more about Weebit’s design expertise, read this recent blog on our smart algorithms.

Ultra-low-power NVM
While the factors impacting NVM power consumption can vary widely based on application, Weebit ReRAM is shown to consume significantly less Read, Write and Standby power than embedded flash and other NVMs, contributing to longer battery life for many devices. The low voltage levels used for memory transactions, coupled with its fast memory access time, greatly reduce the overall power consumed by Weebit ReRAM.

Weebit is also shown to be a ‘greener’ type of NVM compared to other technologies. An environmental initiative we completed with our partner CEA-Leti earlier this year examines the environmental impact of Weebit ReRAM compared to MRAM. You can read about that study here.

The post How Low Can You Go?<br>An Inside Look at Weebit ReRAM Power Consumption appeared first on Weebit.

If you’ve ever watched a Formula 1 race, you may have wondered how the cars reach race speeds up to 360km/h (223mph). Part of the magic is of course the very advanced and powerful engines. The design of F1 engines is extremely precise, enabling these sophisticated machines to be compact, lightweight, and highly efficient. However, no less important are all the other elements surrounding the engine that are designed to maximize its efficiency.

Above: A video that breaks down the high-level design of an F1 car.

In the video above, you can see how every single element of each tiny system in the vehicle is painstakingly designed to optimize airflow, decrease heat and weight, maintain a low center of gravity, generate more horsepower, maximize fuel usage, stabilize the driver and, together with the engine, meet the many other goals needed to be an F1 contender. If you’re interested in the math behind how the F1 engines can efficiently reach 1,000 HP, you can check out this video.

While Weebit isn’t designing race cars, we are very focused on optimizing the performance of our ReRAM. As such, we focus not only on the performance of the ReRAM array, but also use a broad range of smart engineering techniques in the Weebit ReRAM module which surrounds our memory array, to maximize that performance.

At the recent 15th IEEE International Memory Workshop (IMW) 2023, Bastien Giraud, a research engineer from CEA-List, presented, “Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro,” a new paper written by CEA-List, CEA-Leti and Weebit.

The paper shares various design assist techniques used in development of the Weebit ReRAM module – some of the important methods that help us to optimize performance parameters. This includes state-of-art custom programming strategies including Read-Before-Write (RBW), Current Limiter (CL), Write Termination (WT), Write Verify (WV) and Error Correction Code (ECC), driven by a flexible Smart Write Algorithm (SWA). The authors describe how each one of these techniques enhances the intrinsic performance of the ReRAM.

Above: A die photograph and technology cross section of the test chip (memory module) described in the paper.

A key part of the equation is the SWA, which is a programmable algorithm embedded in the design. With the SWA, the writing parameters such as the Set and Reset voltages, the write pulse width, limit current and write termination current can be widely and independently tuned. This means that there is a wide array of different voltages that can be used for Set and Reset (1,024 different combinations). And there is a similarly wide range of pulse width, limitation and termination settings, as well as other variables – all to enable the best possible combinations for a target application. The parameters are programmable to adapt the SWA patterns to the specific requirements.

For testing purposes, the ReRAM module was integrated into a test chip which emulates system functions. Within the test chip, a RISC-V core optimizes the SWA parameters with software tuning loops during early life of the chip, and the ReRAM itself stores the parameters afterwards. This level of flexibility enables each setting to be determined individually to maximize reliability.

Above: a diagram of the embedded SWA.

The paper explores the individual and cumulative benefits from most common programming techniques deployed in the ReRAM macro. Each technique acts differently on energy consumption, access time, bit error rate (BER) and read margin. And altogether, the techniques, mastered from the flexible smart programming algorithm, efficiently counteracts the inherent variability of the ReRAM.

Compared to the original performance of the ReRAM macro, using the combined design techniques resulted in overall improvements of 87% in energy savings and a reduction of 55% on access time. You can read the paper here.

As we get ready for the next Formula 1 races, and as the teams from Alfa Romeo, AlphaTauri, Alpine, Aston Martin, Ferarri, Haas F1, McLaren, Mercedes, Red Bull Racing, and Williams continue to tweak their car designs, at Weebit we are continuing to explore and implement design techniques to further optimize our ReRAM performance.

The post ReRAM Gets a Boost<br>from Smart Algorithms appeared first on Weebit.

A bit of background

The overall contribution of the semiconductor industry to global greenhouse gas (GHG) emissions is increasing as demand for semiconductors continues to grow. To mitigate negative impacts, environmental programs are extremely important for all players in the semiconductor ecosystem. In addition to CO₂ emissions, semiconductor manufacturing can use a significant amount of energy, water, rare natural resources, and chemicals, which can contribute to global warming. The choices semiconductor companies make in design and specification phases, including their memory technology choices, are key to reducing a company’s overall carbon footprint.

MRAM is effectively the only other kind of emerging NVM that is commercially available today at foundries. It stores data as resistance using magnetic fields (versus ReRAM which stores it as resistance of a solid dielectric material, and flash which stores data as electric charges). MRAM has high endurance and is more often used as a replacement for embedded SRAM than for embedded flash. Still, there are companies using MRAM today as a replacement for embedded flash that do so because until now there hasn’t been a production-ready alternative at smaller geometries.

Compared to MRAM, Weebit ReRAM is the logical choice for embedded applications, with the number one reason being ease of manufacturing. Weebit ReRAM requires significantly fewer layers and masks and doesn’t use exotic materials or special equipment, so it can be manufactured in the standard CMOS production line and doesn’t require designated cleanroom facilities. All this translates to lower costs. MRAM adds an estimated 30-40% to wafer cost, compared to ReRAM’s 5-7%. We will go into more depth on MRAM in a future article, but for now, suffice it to say that ReRAM has a long list of advantages over MRAM, and in our new study, we’ve outlined yet another advantage – ReRAM is much more ecologically friendly! 

What we looked at

The team at CEA-Leti estimated the contribution of both OxRAM and MRAM to climate change, focusing on the production flows of each technology. To enable a fair comparison, the study looked at each technology in an identical die area in a similar process node and considered only the memory cell portion. They looked at raw materials and manufacturing processes (cradle to gate) without including infrastructure and abatement. Scroll to the end of the article to learn more about the data collection for the study*.

Key results

The study found that on all measured parameters, OxRAM demonstrated a better GHG related profile than MRAM. Below we’ve listed some of the key results.

ReRAM demonstrated the following benefits over MRAM:

• 30% reduction in GHG emissions
• 41% reduction in water use
• 53% reduction in use of minerals and metals
• 36% less electricity to process

The importance of critical materials

One of the key study findings is that the MRAM flow contains 2X more critical raw materials than the OxRAM flow. As defined by the European Union, the two main factors that define the criticality of a material are supply risk and economic importance. Supply risk is determined by criteria including supply concentration, import reliance, governance performance of suppliers, trade restrictions and criticality of substitute materials. Economic importance is based on a material’s added value, importance in end use applications, and the performance of any substitute materials. In the below chart you can see the criticality of various materials used in semiconductor manufacturing.

Many of the materials required for MRAM are at high supply risk, and some – like magnesium, platinum and cobalt – are critical in terms of both supply risk and economic importance. Any disruption of access to such materials, whether from political challenges, extreme weather, COVID lock-downs, or other issues can put a project at risk. In addition, the borates that are used in MRAM manufacturing have a very poor recycling input rate (less than 1%) – yet another consideration when looking at environmental impacts.

The bigger picture

There are many environmental considerations that come into play for semiconductor technologies such as NVMs. In our study, we specifically looked at the memory cells and circuits themselves, without accounting for the rest of the chip (e.g., microcontrollers) or the environmental impacts of the product lifecycle, such as power consumption during its usage and end-of-life recycling.

The results we’ve shown here can provide customers with confidence that when they are choosing an alternative to flash for their next design, they can not only count on the many known advantages of ReRAM, but they now know that Weebit ReRAM has a lower environmental impact and less supply chain risk than MRAM.

* Notes about the study

• Primary data: All data about the steps of the production flow came from internal collection by Leti, which has broad expertise in both MRAM and ReRAM. Quantity and types of materials used (metals, chemicals and gases), water consumption, energy consumption, and air/water emissions were measured by Leti.
• Secondary data: All raw materials data came from the Eco Invent database.
• Production is in France and therefore the energy mix is the French mix.

The post Weebit ReRAM: <br>NVM that’s better for the planet appeared first on Weebit.

What is a PMIC?

One of the first things to know about a PMIC is how to say it. You can say each letter separately, or you can call it a “P-mick”. At only two syllables, it’s easier to say, and if you’re reading this article aloud to your colleagues, they’ll be very impressed by your knowledge.

PMICs are integrated circuits (ICs) that regulate and control the power in an electronic system and often incorporate multiple power management functions in one chip.  For mobile and other battery-operated devices like wearables, hearables, sensors, and IoT devices, PMICs can help extend battery life, decreasing battery size to achieve the smallest possible form factor. In high-performance, computationally intensive platforms, PMICs are used to maximize performance per watt while increasing system efficiency.

A PMIC is responsible for controlling the flow and direction of electrical power within a device

PMICs are ubiquitous – they are used in just about every electronic system. At the most basic level, the PMIC controls the flow and direction of electrical power within a system. It sets the voltage levels (e.g., 3.3V, 5V, etc.) for each of the chips in a system, including CPUs, digital-to-analog converters (DACs), analog to digital converters (ADCs), and input/output (I/O) devices. Because voltage often varies between these components, many products use multiple voltages internally, and the PMIC makes sure the correct voltage is supplied to each one. The PMIC also acts as a conduit from the external power source – such as a battery or wall outlet – to the various components.  Because of the combination of functionality that is required in a PMIC, a BCD (Bipolar-CMOS-DMOS) technology is often used. This single process makes it possible to integrate analog components (bipolar), digital components (CMOS) and high-voltage transistors (DMOS) on the same die.  This is a complex technology that provides advantages for PMICs and a large set of analog and power components to the designer.

All this means that a PMIC’s job is more challenging in more complex products. Today, PMICs for complex systems have pre-programmed and adjustable functions to address the many disparate requirements they may face, and they are often field upgradeable as well.

A Growing Market

According to a 2021 report from Yole, the PMIC market will grow to more than US$25.6 billion by 2026, with mobile/consumer representing the largest segment. Multi-channel PMICs – those that need various voltages to power various loads – are dominant in these markets.

The same report predicts automotive and industrial applications will grow most quickly during that time. In automotive, this is driven by adoption of multi-channel PMICs widely used in advanced driver assistance systems (ADAS), as well as electric vehicles where PMICs manage the power flow through the EV battery.

There are also opportunities for highly integrated PMICs in other segments such as industrial, telecom, and medical applications.

NVM in PMICs

Power management as a function has been used for decades. Up until the mid-1990s, the primary goal was to trim voltages to fit product requirements, and this was handled as a simple analog function. In the mid-1990s, as electronic complexity increased, PMICs began to manage this function using very simple EEPROM, a basic type of read-only Non-Volatile Memory (NVM) to store analog calibration and trimming data. One-Time-Programmable (OTP) NVM was also used for this function, but since trimming often requires iterative voltage adjustments, multiple banks of NVM were needed when using OTP.

Starting in the early 2000s, as companies started integrating more and more digital functionality into one chip (a System-on-a-Chip or SoC) to meet performance, cost and power consumption goals, the function of the NVM inside of PMICs began to evolve and it continues to do so today. While still used for trimming voltages, in today’s highly integrated SoCs, embedded NVM is a critical block within the PMIC, used to store controller code and configuration data, as well as unique IDs.

Some PMICs today also require integration of a microcontroller (MCU) for added intelligence, including smart sensing and measurement in ultra-low power IoT products. These highly integrated systems not only need to store data and boot code, but must also run firmware updates, requiring high-performance, low-power NVM.

As NVM plays an increasingly critical role in these chips, it has moved from storing hundreds of bits to thousands of bits to tens of thousands of bits – potentially even a million bits.

Of course, not every PMIC needs this level of complexity. Some systems need only very simple voltage regulation, and simple PMICs with small NVM can do this. This is why NVM for PMICs can range from very simple EEPROM or OTP NVM for small, simple requirements; to Multiple-Time Programmable (MTP) for a small programmable/reconfigurable NVM; to embedded flash for more robust needs. There are power, area, performance and cost tradeoffs which designers must consider alongside power management requirements.

Embedded Flash in PMICs

When it became apparent in the early 2000s that a more robust NVM solution was needed for a growing number of PMICs, embedded flash was the only available option, so that’s the way the industry moved. Unfortunately, the addition of flash introduced a great deal of complexity and expense, starting with the addition of between seven and 11 extra masks into an already complex manufacturing process.

Another complication is that embedded flash must be integrated in the Front End of Line (FEOL) of the manufacturing process where other analog and power components are also integrated. Because the BCD process integrates a variety of different components on a single die, it requires careful balancing of the different design needs of each device type.

At the same time, Flash requires careful integration to make sure it works reliably within a design – often based on past experience and best practices. To accommodate it, companies must make technology design trade-offs that sometimes compromise the other analog components in the FEOL. In this way, flash plays an outsized role in driving the integration strategy of the whole chip. This is obviously not ideal since the compromises designers must make to accommodate flash can lead to overall degraded performance, larger size, and higher cost.

Flash has other limitations including a lack of robustness in harsh environments, which often requires building costly redundancy into the design. Importantly, the integration cost of embedded flash increases with each process shrink, an obvious challenge as companies move to more advanced process geometries. All this means that the industry is looking for new NVM solutions.

Emerging Memories for PMICs

When considering alternatives, the first consideration is whether an NVM is integrated in the back-end-of-line (BEOL), where no compromises are needed with other analog components. Using a BEOL NVM allows full optimization of analog components, and it simplifies adoption into new fabs (it can be adopted once for a geometry and it will work with all the different variants, unlike flash which must be adapted to each variant). A BEOL memory is the best alternative to embedded flash for PMICs, but it must be small and cost-effective.

Weebit ReRAM is a Back-End-of-Line (BEOL) technology, enabling full optimization of analog components, and simplifying adoption into new fabs

As a BEOL NVM technology, Ferroelectric RAM (FRAM) is one option that companies can consider. However, FRAM is unable to handle the high temperatures needed in PMICs (up to 150 degrees Celsius). It also requires exotic materials and new fab equipment – neither of which makes sense for an analog chip like a PMIC. Another option is Magnetoresistive RAM (MRAM). MRAM is also a BEOL technology and, in most cases, it can handle high temperatures. However, MRAM is complex and expensive from a capital expenditure as well as manufacturing standpoint, requiring expensive additional tools and masks, which is not a good fit for the analog market.

The answer? Weebit ReRAM. As a small and cost-effective BEOL technology, it checks all the boxes for NVM in PMICs.

Weebit ReRAM checks all the boxes for NVM in PMICs

Toward Net Zero

The low power consumption of Weebit ReRAM is an important advantage for PMICs, especially as societies across the world look for ways to decrease their carbon footprints. PMICs can keep power consumption and dissipation in electronic systems as low as possible – both active (when it’s on) and leakage (when it’s off). With PMICs designed from top to bottom for high efficiency – including ultra-low-power NVM, it’s possible to have a real impact on this critical issue.

Weebit and our R&D partner CEA-Leti are currently conducting an environmental initiative that will analyze the environmental impact of Weebit’s ReRAM compared to other NVM technologies.

With its unique combination of advantages, Weebit ReRAM is the logical alternative to embedded flash for the next generation of PMICs.

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One of the most important parts of a good screenplay, novel or other type of story is character development. If you’ve seen the Indiana Jones movies, you’ll probably recognize the character described in the quote excerpts above, which are from a long discussion between George Lucas, Steven Spielberg and Larry Kasden as they initially developed the Indiana Jones character in January 1978. A transcript of that discussion is available (registration is required) that shows just how much thought went into creating the personality, back story, motivations, and other traits of the character.

This description was not part of the screenplay itself (which is also available at the above link), but it represents some of the critical preliminary work done to make the character come to life. Such a description is critical in development of a realistic screenplay (and ultimately a movie) because it provides guidelines for the hero’s behavior in any possible situation, ensuring consistency and resulting in a believable character.

Indiana Jones image courtesy of http://www.theraider.net

Similarly, although using a much more rigorous and scientific process), semiconductor devices must be characterized. For a semiconductor device, ‘characterization’ is the testing process which assesses exactly what the chip looks like and how it functions under any given condition.

 Semiconductor Device Characterization

The semiconductor characterization process is used to develop the nominal and maximal boundaries of a device’s behavior across a range of conditions. It tests the assumptions of the initial device definition and specification while making various tweaks and optimizations. Specifically for NVM devices, the characterization process also involves employing smart algorithms to ensure the spec boundaries. Similar to the specification we receive when we buy a car or other complex product, the end result is a final specification that enables customers to understand the device’s expected behavior and limitations so they know what they can and can’t do with it when they design their application. The customer will use the boundaries set through the characterization process when designing their own product or application.

Characterization must be done on every new semiconductor design when its first silicon units arrive after fabrication. The process focuses on performing very accurate electrical measurements to gather as much data as possible.

In a previous article, we discussed qualification, a process focused on stress testing samples from multiple production lots to ensure the technology is robust over a product’s expected life span. In contrast, the characterization of a device is used to:

• Assess functionality for parameters such as yield, performance and stability
• Determine optimal operating conditions – looking at the immunity to process, voltage and temperature variations
• Discover potential problems and sensitivities – to correct any process errors
• Verify the final specification limits and production test program – used for further testing and reliability qualification

While characterization and qualification are different processes, they happen in tandem and data feeds between the two. For example, when we find optimal or boundary conditions through characterization, we apply those conditions using various stresses during qualification.

 Answering Key Questions

As we go through the characterization process with our ReRAM module, we are aiming to address a range of key questions. While a technology like ReRAM starts with few single cells, we want to know how those cells will behave if we put millions, tens of millions or more of them together on the same chip. What does their distribution look like? What is their cell-to-cell variability? For example, in the same array, do we have cells that can be written faster than the rest of the cells, while other cells are slower?

Beyond the chip, we need to understand how the on-chip ReRAM cells behave across an entire wafer. What is the die-to-die variability? Is the performance uniform? What is the die yield (percentage of good dies per wafer)? Then we look at the variance between different wafers and different production lots. Does each lot have different results? What is the lot-to-lot variability? Is there any sensitivity to process variations?

The Characterization Process

To answer these critical questions, we begin by building a system to cover all operating conditions. The main challenge with characterizing a chip based on a new technology like ReRAM is to create the specific methodologies that suit that technology. We start with methodologies originally developed for other NVM technologies such as flash memory, and then we tune those for our technology. For the tests, we use an evaluation board designed specifically to test and operate the device, as well as a production tester (Automated Testing Equipment or ATE).

Before jumping in, the first thing we must do is verify that there aren’t any process issues that impact the wafers. This is especially important for new technologies. Once the technology is verified, we then move on to testing the basic functionality of the chip. In the case of ReRAM, this means measuring the initial characteristics of the memory cells such as initial resistance. We must also make sure we can access each of the memory cells in every chip, and that we can write, read and erase each cell multiple times. We also confirm that the cells behave according to expectations in terms of electric current and voltage levels as well as timing.

We check all these parameters using code and test programs that automatically perform operations on the ReRAM cells/arrays. The tests use various patterns of zeros and ones to ensure the device can correctly store and retain the information, and we vary the data patterns to make sure each cell can handle any combinations of data types.

After testing several units, we move on to testing a larger amount of dies and collect statistics based on a broad range of electrical and physical conditions. This includes environmental conditions such as temperature, since we want to make sure customers can use the device reliably in products that are used not only at room temperatures but also in extremes – whether it be outdoors in the desert or in the arctic tundra.

 Characterizing the Weebit ReRAM Module

Weebit is currently characterizing our embedded ReRAM module developed with our partner CEA-Leti. The module includes the ReRAM array as well as control logic, decoders, IOs (Input/Output communication elements) and error correcting code (ECC) as well as patent-pending analog and digital smart circuitry, implemented 130nm. This process is happening concurrently with the module’s qualification (you can read here about our initial qualification results here).

Our team of product and test engineers are working alongside engineers from CEA-Leti’s LIST design team in a new lab in Israel that we established for this purpose. We expect to have final results before the end of 2022.

The post The Importance of Character Development:<br>Semiconductor Characterization Explained appeared first on Weebit.

It takes a lot of work to ensure you end up with perfectly formed, equally portioned, evenly baked cookies that look and taste the same every time.

It’s not just the actual ingredients that matter, although those are clearly important (at Weebit we really like chocolate chips), it’s also the specific amounts of each ingredient, the baking time and temperature, and even the particular baking sheet and oven you use. It’s also important that you use a tool like an ice cream scoop to ensure each cookie is the same size. Do you use a cookie press? Roll the dough into balls? Once you have the process down, you’ll need to bake a number of batches under different conditions to make sure they turn out right every time. This is how you create the perfect cookie recipe.

The same is true in semiconductor manufacturing – which is of course quite a bit more complex and sensitive. When a fab gets ready to start manufacturing a new technology, it must work closely with the technology developer to create the perfect recipe – including the materials, process, tools and equipment, and other variables. They must then work together to thoroughly test the technology to ensure high-quality, consistent, and repeatable results.

This process is called Technology Transfer, and in this article, we’ll share with you some of the ingredients that go into making it happen smoothly.

How to Start the Technology Transfer Process?

The technology transfer process begins, as you might expect, with the signing of an agreement between a semiconductor technology provider and a semiconductor fabrication facility (fab).

As soon as we signed our first commercial agreement a few months back with US-based foundry SkyWater Technology, we kicked off the technology transfer process to SkyWater from Weebit and our R&D partner CEA-Leti (at whose facilities we’ve been manufacturing parts to date). The many steps of the process of migrating our ReRAM technology from the development fab to the production fab will continue throughout the coming months.

The initial technology transfer planning stages include a thorough investigation of the toolsets, materials and process flows used by the different companies. While there are often commonalities and crossovers, it is highly unlikely that the equipment and specific processes will match exactly. There will be different equipment, process flows, materials, recipes, quality stacks for specific toolsets, and so on. And even when any of these things are ‘the same’ between different fabs, there might be variations.

In developing our ReRAM technology, we took this into account at the outset. That’s why we not only focused on developing the best technical solution; we developed our ReRAM to be commercially viable. Part of this was choosing the most common materials and equipment used in fabs today. This ensured that when the time came, this part of the technology transfer process would be as straightforward as possible. If we had used rare materials or unique tools, this would have made it much more complex, expensive and risky.

Ensuring Ease of Transfer

While the technology transfer to SkyWater is the first for Weebit, the Weebit and CEA-Leti team members who are managing the transfer have been through this process many times before. That doesn’t mean the process will be fast or easy, but it means the team knows how to prepare for it, and how to execute it.

From the outset of our ReRAM development, the Weebit and Leti R&D teams have ensured that technical data is scientifically gathered, organized, and documented. In addition, Leti has a clear methodology in place based on its deep experience in transferring processes to production fabs. This is one of the many positive aspects of our R&D relationship with Leti. With their methodology as a starting point, the team members then added their own unique input from their past experience and previous technology transfer work, filling out an already robust methodology.

The Complexity of Technology Transfer

The specific process steps used in the development of Weebit’s ReRAM are part of our ‘secret recipe’ so we can’t go into too much detail, but the steps include things like the thickness, density, stress, uniformity, composition, layer stress, surface roughness and layers/process order. At each step, there are quality parameters that the team must adhere to, ensuring that the same parameters are used at both the Leti development fab and SkyWater’s production fab.

The process is so complex and looks at so many variables that even things like tool maintenance are thoroughly documented. For example, every time a certain number of wafers is run through a piece of equipment, it will need to be cleaned, or parts must be replaced. While such schedules are specified by the tool vendor, they can be affected by different processes, amounts of materials, and so on, and must therefore be part of the transfer.

In the technology transfer process, even the smallest variation is important. This can include anything from stress at a certain point in a metal layer to simple things like water evaporation. Everything must be considered and documented.

Once the ReRAM process is transferred, testing begins. Testing is done using a vehicle which basically comprises a mask set with the memory inside—in this case our embedded module. Beyond this, we will move onto the next step – technology qualification (more on this in a future article).

Coordinating across the globe

The team involved in transferring Weebit’s ReRAM to SkyWater is located in multiple locations. The core Weebit team is in Israel, the Leti team is in France, and the SkyWater team is primarily located in Minnesota in the United States. The combined team comprises experts in design and process integration, as well as experts in testing and qualification.

Daily emails, electronic data transfers, weekly Zoom calls and monthly management meetings keep the process moving along. The pandemic has complicated things slightly in terms of in-person coordination, but it hasn’t impeded progress, and we are progressing as planned.

Perfecting the recipe

While we proceed with the technology transfer to SkyWater, we are also focused on perfecting the recipe for memory cells with even better performance. We are pleased to be continuing our work with the experts at Leti and are delighted with the new relationships we’re building with our partners at SkyWater.

We will continue to provide updates as we progress further down the path.

In the meantime, if you’re looking for that ‘perfect’ chocolate chip cookie recipe, you can find the best cookies ranked on various key criteria by a group of cookie lovers here. Enjoy!

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